Our design tools offer extensive support for advanced technology and high speed board design, with constraints (design rules) that allow tight control of critical sections of your layout. We also offer pre- and post-layout simulation for complete peace of mind.
stackup: meeting your electrical performance requirements starts with the stackup, and we will work with you and your preferred board fabricator to ensure that critical impedance requirements are met.
spacing: default (manufacturing minimum) spacing rules may be specified between all design elements (traces, vias, surface mount and through-hole pads, copper pours, holes); these may be overridden as required for nets, differential pairs, busses and net classes
same net spacing: length matching and tuning can result in “serpentine” routing where extra length is added to a trace; in these cases, signal integrity concerns may require that the looping patterns within the same net are subject to a specific minimum spacing – typically this is 2x to 4x the vertical distance from the layer to an adjacent reference (ground or power) plane
physical: physical characteristics can be specified for individual nets, differential pairs, busses and net classes – including nominal width, neck width and maximum length, spacing (for differential pairs) and allowed via types.
differential pairs: pairs of nets can be treated as a differential pair, with a specified nominal width and spacing, and control of phase tolerance (maximum delta between the lengths of the pair) and the maximum length of uncoupled sections (typically at the source or destination)
busses: groups of nets can be named and visualised as a bus during design planning
net classes: nets can be grouped in “classes” and these can be used in turn to apply special spacing criteria between classes that take precedence – for example between differing clock domains
absolute propagation delay: trace lengths can be constrained to stay within a specified minimum and maximum limits.
relative propagation delay: trace lengths can be constrained with respect to a target trace – for example data with respect to DQS in the case of DDR memory busses;
scheduling: the connection sequence of critical nets can be specified explicity – for example the address/command/control signals of a DDR3 memory interface can be forced to flow from the controller to the near end and then the far end of the memory devices.
stubs: typically used in combination with scheduling, stub lengths can be constrained as required to meet signal integrity requirements
constraint regions: specific areas can be specified within which different physical and spacing constraints may be applied, for example in the escape region of a BGA